发明名称 METHOD FOR FABRICATING A MICROELECTRONIC DEVICE USING WAFER-LEVEL ADHESION LAYER DEPOSITION
摘要 A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
申请公布号 US2003013232(A1) 申请公布日期 2003.01.16
申请号 US20010903025 申请日期 2001.07.11
申请人 INTEL CORPORATION 发明人 TOWLE STEVEN;SAKAMOTO HAJIME;WANG DONGDONG
分类号 H01L23/485;(IPC1-7):H01L21/44;H01L21/48 主分类号 H01L23/485
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