发明名称 Etch stop in damascene interconnect structure and method of making
摘要 An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of interconnect structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.
申请公布号 US2003013292(A1) 申请公布日期 2003.01.16
申请号 US20020245508 申请日期 2002.09.18
申请人 发明人 FARRAR PAUL A.
分类号 H01L21/768;H01L23/532;(IPC1-7):H01L21/476 主分类号 H01L21/768
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