| 摘要 |
PURPOSE: A bit line decoding scheme and circuit for dual bit memory with a dual bit selection are provided to selectively connect two bit lines to two intermediate data lines and selectively connect the intermediate data lines to sense amplifiers through decoding transistors. CONSTITUTION: The device comprises a flash memory array with a plurality of dual bit memory cells(10), a first decoder unit(11) connecting a voltage to bit lines of the memory array, the bit lines function both as source lines and as drain lines, a second decoder unit(12) connecting the bit lines to a plurality of intermediate data lines, a third decoder unit(13) connecting the plurality of intermediate data lines to a plurality of data lines connected to a plurality of sense amplifiers.
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