NEW MICROCELL REDUNDANCY SYSTEM FOR HIGH PERFORMANCE eDRAM

摘要

PROBLEM TO BE SOLVED: To provide a new microcell redundancy system for a wide band width embedded DRAM having a SRAM cache interface. SOLUTION: For each bank of microcell array units comprising the eDRAM, at least one microcell unit is prepared as the redundancy to replace a defected microcell within the bank. After array testing, any defective microcell inside the bank is replaced with a redundancy microcell for that bank. A fuse bank structure implementing a lookup table is established for recording each redundant microcell address and its corresponding repaired microcell address. In order to allow simultaneous multi-bank operation, the redundant microcells may only replace the defective microcells within the same bank.