发明名称 LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a layout method for a semiconductor integrated circuit which can lessen a noise level if a signal is superimposed by the noise generated along parallel wiring which is adjacent to the signal wiring, and prevent the signal delay from being changed by the noise. SOLUTION: Cross talk capacity in nodes b1, c1 are approximately half of the cross talk capacity in a conventional case, and cross talk noise, which is almost proportional to the cross talk capacity, lessens. In addition, the cross talk capacity in the nodes b1, c1 are equal and drive potential of an inverter, which is inserted in unit parallel wiring, is also equal, and the cross talk noise en1, en2 are equal in size and also in a reverse phase. Because of this, the cross talk noise enl and the cross talk noise en2 are mutually off-set in the node c and the cross talk noise superimposing the signal lessens ultimately to a larger extent.
申请公布号 JP2003006262(A) 申请公布日期 2003.01.10
申请号 JP20010190821 申请日期 2001.06.25
申请人 NEC MICROSYSTEMS LTD 发明人 TANAKA MIKITO;KATO AKITOSHI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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