| 摘要 |
A method and structure for a dynamic random access memory chip includes memory element arrays having bitlines, a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, an equalizer circuit connected to the multiplexors and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.
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