METHOD OF MEASURING COMBINED CRITICAL DIMENSION AND OVERLAY IN SINGLE STEP
摘要
A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising:a) a center feature section that provides a critical dimension point along a given axis;b) plurality of smaller sections positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; andc) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.
申请公布号
WO03003122(A2)
申请公布日期
2003.01.09
申请号
WO2002US19091
申请日期
2002.06.17
申请人
INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人
COMMONS, MARTIN;MONO, TOBIAS;KLEE, VEIT;POHL, JOHN;WENSLEY, PAUL