| 摘要 |
PURPOSE: An apparatus for generating equalization and precharge control signals of a data bus is provided to improve reduction of margins of an equalizing time and a precharge time in a data bus by controlling differently an enable time and a disable time of equalization and precharge of the data bus in a writing process and a reading process. CONSTITUTION: The first pulse generation portion(10) controls a rising time of a data bus precharge control signal(dbeq) according to an inputting state of a y pre-pulse signal(yprep) and a read signal(rd). The second pulse generation portion(20) controls a falling time of the data bus precharge control signal(dbeq) according to an output of the first pulse generation portion(10) and the read signal(rd). The first pulse generation portion(10) is formed with the first NAND gate(nd1) for receiving the y pre-pulse signal(yprep), the first delay portion(D1), an AND gate(ad1) for receiving a delay signal of the first delay portion(D1), the second delay portion(D2), an inverter(iv3), and a second NAND gate(nd2). The second pulse generation portion(20) is formed with a NAND gate(nd3), the third delay portion(D3), an AND gate(ad2), the fourth delay portion(D4), an inverter(iv4), and the fourth NAND gate(nd4). A buffer portion(30) buffers an output of the third NAND gate(nd3) and outputs a data bus precharge control signal(dbeq).
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