| 摘要 |
A signal processing circuit and an information recording apparatus in which a memory section has two storage areas each of which has a capacity for at least one block of record data and which are alternately switched to a parity-added data storage area where record data added with a parity by a parity adding section is stored and a transmission area into which the parity-added record data is read and transmitted by a transmission section, and the parity adding section starts adding the parity to record data upon reception of record data for one row of error correcting codes.
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