Low power architecture for register files

摘要

A low power architecture for register files is provided. A decoder receives a specified bit address divided into a first input and a second input. The decoder is split into a first stage and a second stage. A pre-decoder in the first stage receives the first input, identifies a local bitline that is accessed, and outputs a first signal to a register file array. A post decoder in the second stage receives the second input and the first signal, processes the identification of the local bitline, and generates a second signal to be sent to the register file array. A delay synchronizes the first signal and the second signal so that both signals reach the register file array simultaneously.