发明名称 |
Low-power semiconductor memory device |
摘要 |
Sense amplifiers are alternately disposed on both sides of bit line pairs, switch circuits are provided so as to selectively connect two bit lines to a sense amplifier, and connection between a sense amplifier and a bit line is switched in accordance with an operation mode. Memory cells are disposed in rows and columns to satisfy the condition that the memory cells are arranged every other row in the same column. A low-power semiconductor memory device with improved access efficiency is provided due to selective activation of the sense amplifiers for reducing the number of the sense amplifiers activated at a time.
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申请公布号 |
US2003002315(A1) |
申请公布日期 |
2003.01.02 |
申请号 |
US20020230213 |
申请日期 |
2002.08.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OOISHI TSUKASA |
分类号 |
G11C11/401;G11C7/08;G11C7/18;G11C11/406;G11C11/4074;G11C11/409;G11C11/4091;G11C11/4097;(IPC1-7):G11C5/06 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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