发明名称 SYSTEM HAVING A CONFIGURABLE CACHE/SRAM MEMORY
摘要 <p>An apparatus comprising a digital signal processor core having a data port; and a memory system having a plurality of blocks coupled to said data port, where said plurality of blocks are connected in such a way as to provide substantially simultaneous data accesses through said data port to said digital signal processor core.</p>
申请公布号 EP1269328(A2) 申请公布日期 2003.01.02
申请号 EP20010922915 申请日期 2001.03.30
申请人 INTEL CORPORATION;ANALOG DEVICES, INCORPORATED 发明人 RAMAGOPAL, HEBBALALU, S.;WITT, DAVID, B.;ALLEN, MICHAEL;SYED, MOINUL;KOLAGOTLA, RAVI;BOOTH, LAWRENCE, A., JR.;ANDERSON, WILLIAM, C.
分类号 G06F12/00;G06F12/08;G06F13/00;G06F13/16;(IPC1-7):G06F13/00 主分类号 G06F12/00
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