Glitch-less clock selector

摘要

A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare. The new clock signal (MUX output) latches the compare signal and again enables the clock output signal when the new clock signal transitions from a one to a zero. The clock output signal now transitions to a logic one on the next positive transition of the new clock signal guaranteeing glitch free operation. In another embodiment more than two clock signals are selected by providing a multi-bit select signal and registers instead of single bit latches. The select signal is decoded to provide the select signal for the MUX which now selects between more than two clock signals.