APPARATUS FOR GENERATING POWER-UP SIGNAL

摘要

PURPOSE: An apparatus for generating a power-up signal is provided to reduce a variation of power-up time and operate stably a chip by using a diode instead of a resistance in a voltage sense portion. CONSTITUTION: A voltage sense portion(10) is formed with a diode(D1) and a resistance(R3) connected between an external supply voltage terminal(Vext) and a ground voltage terminal(Vss). A level control portion(20) is formed with an NMOS transistor(N2). A power-up signal generation portion(30) is formed with a resistance(R4) and an NMOS transistor(N3) connected between the external supply voltage terminal(Vext) and the ground voltage terminal(Vss). A buffering portion(40) is formed with an inverter(I2) connected between an external supply voltage terminal(Vext) and a ground voltage terminal(Vss) in order to buffer an output signal(det) applied from the power-up signal generation portion(30).