| 摘要 |
The memory circuit (20) of type EEPROM comprises the memory cells (CEi,j) each containing a floating-gate transistor (FGT) and an access transistor (AT) of type MOS, wherein the drain of the floating-gate transistor is connected to the access transistor, and circuits/blocks including a charge pump (PMP), a row decoder (RDEC1), a column decoder (CDEC) and a column latch (LCk) for applying during the erasing phase, the electric voltages (Vcg=Vpp, Vs=0) to the gate and to the source, respectively, of the floating-gate transistors. The row decoder (RDEC1) has another output connected to an access transistor line (ATLi) for applying a determined electric signal (Vat) to the gates of the access transistors of the memory cells to be erased; the voltage value (Vat=0) is different from the programming voltage (Vpp) and is actually the difference between a low or null potential and the source voltage (Vs=0). The source voltage (Vs) is null during the erasing phase. The electric signal voltage (Vat) is null or floating during the erasing phase. The memory cells are arranged according to the word lines (WLi). The row decoder (RDEC1) delivers the word-line selection signal (Vw1) during the erasing phase, the programming and the reading of the memory cell. The row decoder (RDEC1) contains a logic circuit to prevent the application of the word-line selection signal (Vw1) to the process transistor line (ATLi) during the erasing phase, and for applying the electric signal (Vat=0) instead of the word-line selection signal. The memory comprises a control gate transistor (CGTk) for controlling the gates of the floating-gate transistors (FGT) in each row, and circuits/blocks including a current control circuit (ICC) and programming latches (LPIj) for limiting the programming current through the bit line during the programming phase. A supply voltage (Vcc), which is lower than the programming voltage (Vpp), is applied to the gate of the control gate transistor (CGTk) during the programming phase. An Independent claim is also included for method for the erasing and the programming of a memory cell.
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