| 摘要 |
There is disclosed a delay adjustment circuit for a delay locked loop, comprising a delay rough adjustment circuit unit (to which input clock signal CLK-IN, and delay control signals A1 to A6 are transmitted) for selectively obtaining outputs of roughly adjusted delays A and B of two systems having a delay difference indicating a maximum delay value of fine interval delay quantity adjustment from selected ones of selection circuits S1, S3 and S5 of an odd-number stage and selection circuits S2, S4 and S6 of an even-number stage connected to delay elements D1 to D3, and a delay fine adjustment circuit unit (to which delay control signals B1 to B4, and enable signal ENABLE are transmitted) including delay elements FA and FB for receiving outputs of roughly adjusted delays A and B, and selectively carrying out fine interval delay quantity adjustments of the two systems by opposite operations. Outputs of the roughly adjusted delays A and B are switched by delay control signals A1 to A6 when delay differences of outputs of the delay elements FA and FB are equal to each other.
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