| 摘要 |
A phase comparison circuit capable of realizing high-speed response by the PLL circuit in order to realize high-speed reproduction of the signals. An input signal is delayed by a delay buffer in order to produce a delayed signal. Changes in the level of the input signal are detected by a leading edge detection circuit and a falling edge detection circuit, a first and a second edge detection signals are output a control circuit changes the level of an output signal according to these detection signals, a phase comparison circuit compares the phases of the output from the control circuit and the clock signal, and a first and a second control signals are output according to the comparison result. In response to the first and the second control signals from the phase comparison circuit, a charge pump circuit outputs a phase difference signal corresponding to the phase difference between the aforementioned delayed signal and the clock signal and holds the phase difference signal to a high-impedance state when the aforementioned delayed signal and the clock signal are synchronous.
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