发明名称 |
Semiconductor device and method of manufacturing same |
摘要 |
Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1x1018 to 1x1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.
|
申请公布号 |
US6498077(B2) |
申请公布日期 |
2002.12.24 |
申请号 |
US20010816519 |
申请日期 |
2001.03.26 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
UENO SHUUICHI;HORITA KATSUYUKI;KUROI TAKASHI |
分类号 |
H01L21/265;H01L21/336;H01L21/8242;H01L27/108;H01L29/10;H01L29/78;(IPC1-7):H01L21/425 |
主分类号 |
H01L21/265 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|