| 摘要 |
PROBLEM TO BE SOLVED: To provide a SRAM having a dummy circuit in which power consumption is less and a control signal can be generated with optimum timing. SOLUTION: In a static RAM having a memory cell array (10) having memory cells MC arranged at intersection positions of word lines WL and bit lines BL, BLX and a sense amplifier amplifying voltage of the bit lines, the RAM has dummy memory cells DMC selected at the time of selecting a word line. Dummy bit lines DBL, DBLX connected to the dummy memory cells, a timing signal generating circuit (30) generating a timing control signal responding to potential variation of the dummy bit lines, and a dummy memory cell selecting circuit (32) selecting the dummy memory cell being common to the word line group responding to selection of the word line in word line groups having a plurality of word lines. |
