发明名称 |
Timing circuit and method for a compilable dram |
摘要 |
A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.
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申请公布号 |
US2002191448(A1) |
申请公布日期 |
2002.12.19 |
申请号 |
US20010880598 |
申请日期 |
2001.06.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ELLIS WAYNE F.;FIFIELD JOHN A.;HSU LOUIS L. |
分类号 |
G11C7/10;G11C7/22;G11C11/4076;G11C11/4096;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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