DRAW WITH BIT LINE PRECHARGING, INVERTING DATA WRITING, RETAINED DATA OUTPUT AND REDUCED POWER CONSUMPTION

摘要

Various aspects of an integrated circuit having a DRAM are disclosed. In one embodiment an integrated circuit includes a DRAM that (1) pre-charges the bit lines to a voltage that is biased toward a weaker one of two memory cell logic states, (2) selectively stores data in an inverted form that reduces the power needed to refresh such data (in at least one embodiment), (3) retains data in the sense/latch circuits and use such circuits as a form of cache to reduce the frequency that memory cells are accessed and thereby reduce memory access time, and (4) supplies a reference ( e.g., Vpp) from a circuit that employs an alternate, lower power, operating mode (e.g., if the DRAM is in standby) .