REPRESENTING THE DESIGN OF A SUB-MODULE IN A HIERARCHICAL INTEGRATED CIRCUIT DESIGN AND ANALYSIS SYSTEM

摘要

A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set o f all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, an d verification of the block's ancestors in the hierarchy.