| 摘要 |
<p>A semiconductor integrated circuit having a reducied an error rate in judgment of a logic value even when a signal waveform is distorted by a parasitic capacitance in a transmission line or a symbol-to-symbol interference caused in the transmission line. This semiconductor integrated circuit comprises a first judgment circuit for judging the logic value of an input signal in synchronism with a clock signal having a first phase and a second judgment circuit for judging the logic value of the input signal in synchronism with a clock signal having a second phase different from the first phase and changing the judgment criterion on the basis of at least the result the judgment by the first judgment circuit.</p> |
