| 摘要 |
PURPOSE: A circuit and a method for controlling a test mode of a semiconductor device are provided to utilize effectively test modes by inactivating only a particular test mode of a plurality of test modes. CONSTITUTION: A selection portion(500) is formed with the first NAND gate portion(510a,510b,510c,510d) and the second NAND gate portion(520a,520b,520c,520d) in order to select a path of a particular test mode from the first to the fourth test modes. A control portion(600) is formed with the third NAND gate portion(610a,610b,610c,610d) and the fourth NAND gate portion(620a,620b,620c,620d) in order to control an active state or an inactive state of the path of the selected test mode in response to an output signal of the selection portion(500), an active test signal(enable_test), and an inactive test signal(disable_test). An output portion(700) is formed with an S-R latch portion(710a,710b,710c,710d) and a buffering portion(720a,720b,720c,720d) in order to latch and buffer an output of the control portion(600).
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