Semiconductor device enable to output a counter value of an internal clock generation in a test mode

摘要

In a SDRAM, a switch circuit is provided between a memory circuit and a data output circuit. The switch circuit provides data read out from the memory circuit to the data output circuit in a normal operation, and provides a count value of an up/down counter in a DLL circuit to the data output circuit when in a test operation. By monitoring output signals in the test operation, testing of whether the DLL circuit is proper or not can be carried out easily and correctly.