| 摘要 |
An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree; (b) elaborating the parse tree to create a word-oriented netlist; and (c) inferring complex components from the word-oriented netlist.
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