| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide clock supply stopping circuit which does not cause a 'whisker' when a clock stops, does not cause frequency fluctuations when stop is released and can realize low power consumption. SOLUTION: In this clock stopping circuit for stopping operation to an unwanted circuit, etc., a system is provided with a means 1 for synchronizing an enable signal ENA 11 with a clock CLK 10, a means 3 for further making an output ENA 2 that has synchronized the enable signal ENA 11 with the clock CLK 10 to be an enable signal CLKOUT 4 of the clock CLK 10, and a means 5 for performing a prescribed output 15 with an output ENA 2 that has synchronized the enable signal CLKOUT 4 with the clock CLK 10 as a reset signal.</p> |
