| 摘要 |
The present invention includes a system and method for improving phase selection using a phase selector system. An exemplary phase selector system of the present invention includes a high speed phase selector (200) having control logic, XOR gates, and a selector. The control logic uses Gray coding to generate one or more control signals. For example, the control logic uses a 3 bit word to select a phase for clock recovery. A selector (228-240, 250-256) coupled to the control logic determines the phase selected. XOR gates (220, 222, 224, 226) coupled between the control logic and the selector provide eight phases of a clock using four input phases (292, 294, 296, 298) of the clock with inversion. In this manner, a four to one selector can choose one of eight phases from the XOR gates to aid in clock recovery. The selector control logic has a continuous output phase during a change to an adjacent phase, which substantially prevents glitching on the clock. |
