CIRCUIT AND METHOD FOR GENERATING BOOST VOLTAGE IN NON-VOLATILE FERROELECTRIC MEMORY DEVICE

摘要

PURPOSE: A circuit and a method for generating a boost voltage in a non-volatile ferroelectric memory device are provided to perform an operation under a low voltage by performing a stable operation when a power supply voltage region is a wide power voltage region. CONSTITUTION: An address decoder(60) generates an active signal for activating a corresponding address. A word line boost control circuit portion(61) receives a signal of WLBCON and outputs the first and the second control signals(BCON1,BCON2) for controlling a reference point of a word line boost initiate point. The first NAND gate(NAND1) performs a logical operation for the active signal of the address decoder(60) and the first control signal(BCON1) of the word line boost control circuit portion(61). The first inverter(IN1) inverts an output value of the first NAND gate(NAND1). The first ferroelectric capacitor(FC1) is located between the first inverter(IN1) and a CMOS inverter. The second inverter(IN2) inverts the active signal of the address decoder(60). The first NOR gate(NOR1) performs a logical operation for an output signal of the second inverter(IN2) and the second control signal(BCON2). The third inverter(IN3) inverts an output value of the first NOR gate(NOR1). The CMOS inverter is formed with the first PMOS transistor(PM1) and the first NMOS transistor(NM1). The second PMOS transistor(PM2) is operated by an output signal of the CMOS inverter. A level shifter(62) receives a signal of WLPWR and outputs a signal(WLD) for driving a word line driver. A word line driver(63) receives the signal(WLD) of the level shifter(62) and outputs a word line drive signal(WL) to a cell array portion(64).