| 摘要 |
<p>An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase (PHI 1) and offset detection and cancellation occurs on the second phase. On the second phase, the offset cancellation circuit measures the offset created by the amplifier when both differential inputs (202, 204) are connected to a common source (VCMIN). The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the stored adjustment is used to bias the current in one of the two input stages of the amplifier (202, 204), canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled.</p> |
