| 摘要 |
The invention relates to a modification of the standardized peripheral component interconnection (PCI) bus protocol and uses the modified protocol for synchronizing devices of fault-tolerant and distributed computer systems. In a normal event, a target, when it activates a signal DEVSEL# (Fig. 1, CLK 4, low active), has to activate its TRDY# signal after a maximum of 6 clock pulses in order to accept the first item of data of a data transfer. According to the invention, in the event that the target is not ready for a synchronization, the signal DEVSEL# is, in fact, activated, however, the non-activation of TRDY# prevents the acceptance of any data. In order to inform the PCI master of the interruption of the data transfer, the signal STOP# is activated within the first six clock cycles (Fig. 1, CLK 4). The transfer is terminated when the STOP# signal is activated, and the master controller is forced to repeat the transfer at a later point in time. The described protocol process involving interruption results in preventing the target timeout from being active which would signify a loss of data. |
