发明名称 |
Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory |
摘要 |
A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.
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申请公布号 |
US2002180500(A1) |
申请公布日期 |
2002.12.05 |
申请号 |
US20020202091 |
申请日期 |
2002.07.25 |
申请人 |
OKUDA YUICHI;CHIGASAKI HIDEO;MIYASHITA HIROKI |
发明人 |
OKUDA YUICHI;CHIGASAKI HIDEO;MIYASHITA HIROKI |
分类号 |
G11C11/407;G06F1/06;G11C7/10;H03K5/13;H03L7/081;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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