Fast data base research and learning apparatus

摘要

This invention discloses an improved address table apparatus that includes an address bus for receiving input data packets and for hashing a designated bucket number and extracting a key from each of the data packets. The address table apparatus further includes a plurality of memory banks connected to the address bus wherein each memory bank includes a plurality of memory buckets for storing a designation address (DA) and a port number in each of the buckets. The address table apparatus further includes a comparand bus connected to the address bus for receiving the key therefrom. The address table apparatus further includes a plurality of comparators each corresponding to one of the memory banks for receiving the designation address (DA) and the port number from the designated bucket from a corresponding memory bank. The comparators further connected to the comparand bus for receiving and comparing the key to the address from the designated bucket in each of the memory banks. The address table apparatus further includes a result bus connected to the comparators for displaying an output port number from one of the comparators if the key extracted from one the data packets matching the designation address (DA) from one of the designated buckets.