发明名称 |
Pipeline analog-to-digital converter with on-chip digital calibration |
摘要 |
A multi-stage pipeline analog-to-digital converter employs an internal digital domain error detection and calibration algorithm to eliminate accumulated digital truncation errors to thereby improve its accuracy and linearity.
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申请公布号 |
US6489904(B1) |
申请公布日期 |
2002.12.03 |
申请号 |
US20010916553 |
申请日期 |
2001.07.27 |
申请人 |
FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
HISANO SHINICHI |
分类号 |
H03M1/10;H03M1/16;(IPC1-7):H03M1/10 |
主分类号 |
H03M1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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