| 摘要 |
The propagation delay time, power dissipation and silicon area of a double edge triggered flip flop are reduced by utilizing an inverter, a pair of latches, and a two-to-one multiplexer. A first latch outputs a first device signal in response to a first data signal when a clock signal is in a first logic state, and latches the logic state of the first device signal when the clock signal is in a second logic state. A second latch outputs a second device signal in response to a second data signal when the clock signal is in the second logic state, and latches the logic state of the second device signal when the clock signal is in the first logic state. The multiplexer controls the logic state of the flop output signal in response to the logic state of the first device signal when the clock signal is in the second logic state, and in response to the logic state of the second device signal when the clock signal is in the first logic state.
|
