| 摘要 |
PROBLEM TO BE SOLVED: To scale down the chip size of an LSI by efficiently securing the wiring region of the wiring connected to a hard macro and the wiring region of the key power trunk of an internal functional block, in the case of performing the stratified layout of the LSI. SOLUTION: When laying out the LSI 100 having the internal functional block 101 with a built-in hard macro 104 into strata, the in-block power trunk 106 of the internal functional block is made of different wiring layers on the wiring region 105 of the hard macro 104, and the key power trunk 103 of the LSI chip is installed, and the power trunk 106 within the internal functional block is diverted to it. So, the area of the chip can be reduced by the area of the wiring region 105 or thereabouts, and the size of the LSI chip 100 can be scaled down.
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