| 摘要 |
A plurality of input signals to be input to a logic circuit, a verification object, is ranked depending on the degrees of influence the input signals have when vary on operation of the logic circuit. Verification is performed with a free pattern including all possible input patterns given to the input signals sequentially in descending order of the degree of influence. That is, the input patterns are sequentially generated according to preset conditions (the degrees of influence). Therefore, even when forced termination of the formal verification occurs due to insufficient memory of a verification apparatus, the obtained verification results can be kept based on the degrees of influence. This allows easy analysis on the causes of the forced termination, and improvement in verification efficiency. It is possible to estimate the time taken for the completion of the entire verification and the required memory capacity of the verification apparatus.
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