AUTOMATIC TEST CLOCK SELECTION APPARATUS

摘要

An integrated circuit (100) includes circuitry for generating a clock signal (CLOCK) during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector (135). In test mode, an input test clock signal (TEST CLOCK) bypasses the skew corrector (135) via a clock signal source selector (150). The clock signal source selector (150) is controlled automatically by a mode detector (140) that responds to the input clock signals to determine the mode of operation of the integrated circuit (100).