| 摘要 |
An output stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple input registers which hold input addresses and input data words; and a multiplexer circuit, having a plurality of parallel data inputs which concurrently receive the input addresses and the input data words, having control inputs for receiving a sequence of control signals, and which generates serial bit streams by selectively passing bits from the input addresses and input data words in response to the control signals. These serial bit streams from the multiplexer circuit preferably include a first bit stream which defines a data input to an integrated circuit chip that is to be tested, and a second bit stream which defines an expected output from the chip corresponding to the first bit stream. In one particular embodiment, the output stage further includes a memory address generator which generates a sequence of memory addresses, and a memory which receives the sequence of memory addresses, and in response, sends the sequence of control signals from a memory output to the control inputs of the multiplexer circuit. With this embodiment, the memory address generator can include a page register and a counter which together generate the sequence of memory addresses as multiple sub-sequences within respective pages; and the sub-sequences can be generated continuously with no gaps between them so that the serial bit streams from the multiplexer circuit will be generated continuously with no gaps between the serial bits.
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