INSTRUCTION GENERATING METHOD, INSTRUCTION GENERATING METHOD AND INFORMATION PROCESSOR

摘要

PROBLEM TO BE SOLVED: To provide an information processor capable of performing interrupt mask control of a cycle unit without being accompanied with a resources increase such as an instruction memory or the deterioration of a processing speed in an information processor that parallelly performs processing with a plurality of arithmetic circuits on the basis of a LIW(long instruction word) instruction or a VLIW(very long instruction word) instruction that designates a plurality of pieces of parallelly performable processing. SOLUTION: In this information processor which has an interrupt controlling part 1, the instruction memory 2, an instruction decoding part 3, a register part 4, an arithmetic circuit A5 and an arithmetic circuit B6 and can bypass arithmetic operation results of the arithmetic circuit A5 to the arithmetic circuit B6 through a signal line 104 for bypass, a mask signal is outputted to the interrupt controlling part 1 through a signal line 101, when the instruction decoding part 3 discriminates that interrupt mask should be performed from the result of instruction decoding.