PACKAGING OF INTEGRATED CIRCUITS AND VERTICAL INTEGRATION

摘要

A first level packaging wafer (110) is made of a semiconductor or insulating material. The bumps (150B) on the wafer (110) are made using vertical integration technology, without solder or electroplating. More particularly, vias (160) are etched part way into a first surface of the substrate (140). Metal (150) is deposited into the vias (160). Then the substrate (140) is blanket-etched from the back side (110B) until the metal (150) is exposed and protrudes from the vias (160) to form suitable bumps (150B). Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.