| 摘要 |
Described inventions include circuits and methods for generating internal command signals in a semiconductor memory device. A testing time can be remarkably reduced by setting an internal clock signal having a predetermined cycle time shorter than that of an external clock signal of a test equipment, and generating internal command signals of the semiconductor memory device which synchronously respond to the internal clock signal. A command signal decoder composes the plurality of internal control signals. It then generates a test mode enable signal and a reversed test mode enable signal in response to a flag signal of internal address signals for precharging all the banks, and composes the reversed test mode enable signal and the plurality of internal control signals and then generates the internal command signals of the semiconductor memory device. An internal clock generating unit generates a first and second internal clock signals when the test mode enable signal is enabled, and composes the test mode enable signal and one of the internal command signals of the semiconductor memory device and then generates a plurality of internal command control signals which synchronously respond to the first and second internal clock signals.
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