| 摘要 |
<p>To facilitate inter-processor communication between multiple processors in a system and to enable the accessing of a dual port memory, or other system resources, without requiring the memory or the data/address bus to be locked, the present invention provides a semaphore unit (22) that preferably incorporates a shared mailbox architecture (70A, 70B) that, in combination with a set of hardware semaphore registers (68), enables inter-process communication among the multi-processors. Cooperative multitasking may be accomplished through the use of shared mailbox communication protocols while a preemptive multitasking may be accomplished through the use of hardware semaphore registers.</p> |
