| 摘要 |
<p>A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability than N2, an i IN is input to each delay element as the precharge signal, and when the input signal S IN is at a high level, the node A is in the state of a low level and the output terminal OUT is in the state of a high level, the falling edge of the input signal S IN is sequentially propagated by delay elements, and thus a delay signal is obtained.</p> |
