UNA DISPOSICION DE CELULA DE ALMACENAJE.

摘要

1,218,866. F.E.T. storage circuits. INTERNATIONAL BUSINESS MACHINES CORP. 24 April, 1968 [25 May, 1967], No. 19305/68. Heading H3T. [Also in Division G4] In a storage circuit having a bi-stable circuit including two cross-coupled insulated gate field effect transistors Q1, Q2, the load of each transistor includes an insulated gate field effect transistor Q3, Q4 and the gate of each transistor Q1, Q2 iS connected to a semi-conductor switching device Q5, Q6, whereby when both the load transistors Q3, Q4 and the switching devices Q5, Q6 are off the gates of the transistors Q1, Q2 are effectively isolated. The power dissipated in the bi-stable storage circuit Q1,Q2 iS reduced by pulse operation of transistors Q3, Q4. The state of the transistors Q1, Q2 is maintained due to the voltage stored across the circuit capacitances C1 C2. If transistors Q1, Q3 and Q4 are ON and transistors Q3 and Q4 turn OFF then transistor Q1 also turns OFF, but on Q3 and Q4 turning ON again the voltage stored across C2 turns ON Q1 so that the state of the circuit is maintained. In formation may be read out of the store by applying a negative word pulse at 16 which turns ON transistors Q5, Q6-and allows the output at A and B to be fed via 12, 14 to a differential amplifier, the resultant output of which indicates the state of the store. Information may be written in by applying a negative word pulse at 16 and a positive pulse at 12 or 14. The transistors Q1-Q6 may be MOS. In an alternative circuit (Fig. 5, not shown), the gates of transistors Q3 and Q4 may be controlled from separate associative search sources and their drains may be connected to an associative sense line so that the condition of store can be determined by signals applied to the gates of these transistors Q3, Q4. The storage circuits may be connected to form a memory array (Fig. 4, not shown). The write, read and power lines may be transmission lines coupled to the storage circuits by directional coupling techniques. Each row has a common word line and each column has a common sense amplifier connected to the inputs 12, 14. The memory can be powered row by row at different times.