发明名称 Inclusion of global wires in capacitance extraction
摘要 A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.
申请公布号 US6473887(B1) 申请公布日期 2002.10.29
申请号 US20000560065 申请日期 2000.04.27
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DEWEY, III L. WILLIAM;HABITZ PETER A.;SEIBERT EDWARD W.
分类号 G06F17/50;(IPC1-7):G06F9/45 主分类号 G06F17/50
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