发明名称 METHOD FOR PACKAGING WAFER LEVEL
摘要 PROBLEM TO BE SOLVED: To provide a method for packaging a wafer level capable of forming a flip-chip structure having high reliability. SOLUTION: The method for packaging the wafer level comprises the steps of providing a wafer having a plurality of bonding pads in which an inactivated layer formed on the wafer is exposed thereon, and forming an under-bump metal(UBM) on each bonding pad. The method further comprises the steps of forming a stress buffer layer each having a plurality of first openings, and exposing the under-bump metal(UBM) in the first opening. The method also comprises the step of filling solder material in the first opening of the buffer layer. The method also comprises the step of disposing any of a stencil having a plurality of second openings or a patterned photoresist in the second opening on the buffer layer to expose the first opening. The solder material is allowed to reflow. When the stencil is used, the stencil is removed before the reflowing process. Meanwhile, when the patterned photoresist is used, the photoresist is removed after the reflowing process.
申请公布号 JP2002313833(A) 申请公布日期 2002.10.25
申请号 JP20010161381 申请日期 2001.05.29
申请人 APACK TECHNOLOGIES INC 发明人 SHAO TUNG-LIANG
分类号 H01L23/12;H01L21/60 主分类号 H01L23/12
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