发明名称 |
METHOD AND APPARATUS FOR GENERATING AND CONTROLLING INTEGRATED CIRCUIT MEMORY WRITE SIGNALS |
摘要 |
A circuit and method for generating a write enable pulse that is independent of the clock duty cycle and the clock frequency. The circuit includes a pulse generator for generating a pulse in response to a clock signal and a write enable signal generator for generating a write enable pulse. The pulse tracks the leading edge of the clock signal. A logic circuit is coupled to the pulse generator and the write enable signal generator to generate the write enable pulse by combining the pulse and the write enable signal.
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申请公布号 |
US2002154550(A1) |
申请公布日期 |
2002.10.24 |
申请号 |
US20010839441 |
申请日期 |
2001.04.20 |
申请人 |
MA JAMES;KAWAHIGASHI MARK |
发明人 |
MA JAMES;KAWAHIGASHI MARK |
分类号 |
G11C7/10;G11C7/22;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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