| 摘要 |
A circuit having an address circuit and a memory. The address circuit may be configured to (i) receive an address as a parallel input signal and as a serial input signal, (ii) present the address as an output address in one of an asynchronous mode, a synchronous mode, and a shift mode, and (iii) change the second address one by unit in a counter mode. The memory may be configured to receive the output address.
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