| 摘要 |
PROBLEM TO BE SOLVED: To improve yield by preventing wire shorting. SOLUTION: A multilayer interconnection board 2 is provided with a cavity housing a semiconductor chip 1, bonding wirings in three rows around the cavity, and first and second power source electrodes 2c and 2d which are common wirings provided on both sides with a gap 2b in between with respect to the extending direction in the second-row wiring. Further, there are provided a plurality of wires 3 which connect a pad 1a of the semiconductor chip 1 to the corresponding wiring, a sealing which resin-seals the semiconductor chip 1 and the wire 3, and a plurality of bump electrodes provided to the multilayer interconnection board 2. At the end adjoining the gap 2b at the common wiring of the multilayer interconnection board 2, a wiring correction 2h is provided which protrudes from it in the direction across the extending common wiring to correct a bonding coordinate, so that wire shorting caused by wire crossing is prevented. |
